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1 ca3140, ca3140a 4.5mhz, bimos operational ampli?r with mosfet input/bipolar output the ca3140a and ca3140 are integrated circuit operational ampli?rs that combine the advantages of high voltage pmos transistors with high voltage bipolar transistors on a single monolithic chip. the ca3140a and ca3140 bimos operational ampli?rs f eature gate protected mosfet (pmos) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. the ca3140a and ca3140 operate at supply voltage from 4v to 36v (either single or dual supply). these operational ampli?rs are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. terminals are also provided for use in applications requiring input offset voltage nulling. the use of pmos ?ld effect transistors in the input stage results in common mode input voltage capability down to 0.5v below the negative supply terminal, an important attribute for single supply applications. the output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground. the ca3140a and ca3140 are intended for operation at supply voltages up to 36v ( 18v). features mosfet input stage -v ery high input impedance (z in ) -1.5t ? (typ) -v ery low input current (i l ) -10pa (typ) at 15v - wide common mode input voltage range (v lcr ) - can be swung 0.5v below negative supply voltage rail - output swing complements input common mode range directly replaces industry type 741 in most applications applications ground-referenced single supply ampli?rs in a utomobile and portable instrumentation sample and hold ampli?rs long duration timers/multivibrators ( seconds-minutes-hours) photocurrent instrumentation ? eak detectors active filters comparators interface in 5v ttl systems and other low supply voltage systems all standard operational ampli?r applications function generators ? one controls ? ow er supplies ? ortable instruments intrusion alarm systems pinouts ca3140 (metal can) t op view ca3140 (pdip, soic) t op view ordering information part number (brand) temp. range ( o c) package pkg. no. ca3140ae -55 to 125 8 ld pdip e8.3 ca3140am (3140a) -55 to 125 8 ld soic m8.15 ca3140at -55 to 125 8 pin metal can t8.c ca3140e -55 to 125 8 ld pdip e8.3 ca3140m (3140) -55 to 125 8 ld soic m8.15 ca3140m96 (3140) -55 to 125 8 ld soic tape and reel ca3140t -55 to 125 8 pin metal can t8.c tab output inv. v- and case offset non-inv. v+ offset 2 4 6 1 3 7 5 8 - + null input null input strobe inv. input non-inv. v- 1 2 3 4 8 7 6 5 strobe v+ output offset null offset null input - + data sheet march 2002 fn957.6 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ?intersil americas inc. 2002. all rights reserved
2 absolute maximum ratings thermal information dc supply voltage (between v+ and v- terminals). . . . . . . . . . 36v differential mode input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8v dc input voltage . . . . . . . . . . . . . . . . . . . . . . (v+ +8v) to (v- -0.5v) input terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short circuit duration (note 2) . . . . . . . . . . . . . . inde?ite operating conditions t emperature range . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 115 n/a soic package . . . . . . . . . . . . . . . . . . . 165 n/a metal can package . . . . . . . . . . . . . . . 170 85 maximum junction temperature (metal can package). . . . . . . 175 o c maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details 2. short circuit may be applied to ground or to either supply. electrical speci?ations v supply = 15v, t a = 25 o c parameter symbol test conditions typical values units ca3140 ca3140a input offset voltage adjustment resistor typical value of resistor between terminals 4 and 5 or 4 and 1 to adjust max v io 4.7 18 k ? input resistance r i 1.5 1.5 t ? input capacitance c i 44pf output resistance r o 60 60 ? equivalent wideband input noise voltage (see figure 27) e n bw = 140khz, r s = 1m ? 48 48 v equivalent input noise voltage (see figure 35) e n r s = 100 ? f = 1khz 40 40 nv/ hz f = 10khz 12 12 nv/ hz short circuit current to opposite supply i om + source 40 40 ma i om - sink 18 18 ma gain-bandwidth product, (see figures 6, 30) f t 4.5 4.5 mhz slew rate, (see figure 31) sr 9 9 v/ s sink current from terminal 8 to terminal 4 to swing output low 220 220 a transient response (see figure 28) t r r l = 2k ? c l = 100pf rise time 0.08 0.08 s os overshoot 10 10 % settling time at 10v p-p , (see figure 5) t s r l = 2k ? c l = 100pf v oltage follower to 1mv 4.5 4.5 s to 10mv 1.4 1.4 s electrical speci?ations f or equipment design, at v supply = 15v, t a = 25 o c, unless otherwise speci?d parameter symbol ca3140 ca3140a units min typ max min typ max input offset voltage |v io |- 5 15- 2 5mv input offset current |i io |- 0.5 30 - 0.5 20 pa input current i i -1050- 10 40 pa large signal voltage gain (note 3) (see figures 6, 29) a ol 20 100 - 20 100 - kv/v 86 100 - 86 100 - db ca3140, ca3140a
3 common mode rejection ratio (see figure 34) cmrr - 32 320 - 32 320 v/v 70 90 - 70 90 - db common mode input voltage range (see figure 8) v icr -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 v power-supply rejection ratio, ? v io / ? v s (see figure 36) psrr - 100 150 - 100 150 v/v 76 80 - 76 80 - db max output voltage (note 4) (see figures 2, 8) v om + +12 13 - +12 13 - v v om - -14 -14.4 - -14 -14.4 - v supply current (see figure 32) i+ - 4 6 - 4 6 ma device dissipation p d - 120 180 - 120 180 mw input offset voltage temperature drift ? v io / ? t -8--6- v/ o c notes: 3. at v o = 26v p-p , +12v, -14v and r l = 2k ? . 4. at r l = 2k ? . electrical speci?ations f or equipment design, at v supply = 15v, t a = 25 o c, unless otherwise speci?d (continued) parameter symbol ca3140 ca3140a units min typ max min typ max electrical speci?ations f or design guidance at v+ = 5v, v- = 0v, t a = 25 o c parameter symbol typical values units ca3140 ca3140a input offset voltage |v io |5 2mv input offset current |i io | 0.1 0.1 pa input current i i 22pa input resistance r i 11t ? large signal voltage gain (see figures 6, 29) a ol 100 100 kv/v 100 100 db common mode rejection ratio cmrr 32 32 v/v 90 90 db common mode input voltage range (see figure 8) v icr -0.5 -0.5 v 2.6 2.6 v power supply rejection ratio psrr ? v io / ? v s 100 100 v/v 80 80 db maximum output voltage (see figures 2, 8) v om +3 3 v v om - 0.13 0.13 v maximum output current: source i om +10 10ma sink i om -1 1ma slew rate (see figure 31) sr 7 7 v/ s gain-bandwidth product (see figure 30) f t 3.7 3.7 mhz supply current (see figure 32) i+ 1.6 1.6 ma device dissipation p d 88mw sink current from terminal 8 to terminal 4 to swing output low 200 200 a ca3140, ca3140a
4 block diagram schematic diagram a 10 a 10,000 c 1 12pf 5 a 1 1 8 4 6 7 2 3 offset strobe null output input + - 200 a 200 a 1.6ma 2 a 2ma 2ma 4ma v+ v- bias circuit current sources and regulator r 5 500 ? r 4 500 ? q 11 q 12 r 2 500 ? r 3 500 ? q 10 q 9 d 5 d 4 d 3 5 1 8 strobe offset null 3 2 non-inverting input inverting input + - c 1 12pf q 13 q 15 q 16 q 21 q 20 d 8 q 19 q 18 q 17 r 11 20 ? r 9 50 ? r 8 1k r 12 12k r 14 20k r 13 5k d 7 r 10 1k output d 6 4 v- v+ 6 7 dy namic current sink output stage second stage input stage bias circuit d 2 q 8 q 4 q 3 q 5 q 2 q 6 q 7 d 1 q 1 r 1 8k q 14 r 7 30 ? r 6 50 ? note: all resistance values are in ohms. ca3140, ca3140a
5 application information circuit description as shown in the block diagram, the input terminals may be operated down to 0.5v below the negative supply rail. two class a ampli?r stages provide the voltage gain, and a unique class ab ampli?r stage provides the current gain necessary to drive low-impedance loads. a biasing circuit provides control of cascoded constant current ?w circuits in the ?st and second stages. the ca3140 includes an on chip phase compensating capacitor that is suf?ient for the unity gain voltage follower con?uration. input stage the schematic diagram consists of a differential input stage using pmos ?ld-effect transistors (q 9 , q 10 ) working into a mirror pair of bipolar transistors (q 11 , q 12 ) functioning as load resistors together with resistors r 2 through r 5 . the mirror pair transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor (q 13 ). offset nulling, when desired, can be effected with a 10k ? potentiometer connected across te r minals 1 and 5 and with its slider arm connected to terminal 4. cascode-connected bipolar transistors q 2 , q 5 are the constant current source for the input stage. the base biasing circuit for the constant current source is described subsequently. the small diodes d 3 , d 4 , d 5 provide gate oxide protection against high voltage transients, e.g., static electricity. second stage most of the voltage gain in the ca3140 is provided by the second ampli?r stage, consisting of bipolar transistor q 13 and its cascode connected load resistance provided by bipolar transistors q 3 , q 4 . on-chip phase compensation, suf?ient for a majority of the applications is provided by c 1 . additional miller-effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between terminals 1 and 8. terminal 8 is also used to strobe the output stage into quiescence. when terminal 8 is tied to the negative supply rail (terminal 4) by mechanical or electrical means, the output terminal 6 swings low, i.e., approximately to terminal 4 potential. output stage the ca3140 series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the pmos input stage when operating near the negative rail. quiescent current in the emitter-follower cascade circuit (q 17 , q 18 ) is established by transistors (q 14 , q 15 ) whose base currents are ?irrored to current ?wing through diode d 2 in the bias circuit section. when the ca3140 is operating such that output terminal 6 is sourcing current, transistor q 18 functions as an emitter-follower to source current from the v+ bus (terminal 7), via d 7 , r 9 , and r 11 . under these conditions, the collector potential of q 13 is suf?iently high to permit the necessary ?w of base current to emitter follower q 17 which, in turn, drives q 18 . when the ca3140 is operating such that output terminal 6 is sinking current to the v- bus, transistor q 16 is the current sinking element. transistor q 16 is mirror connected to d 6 , r 7 , with current fed by way of q 21 , r 12 , and q 20 . tr ansistor q 20 , in turn, is biased by current ?w through r 13 , zener d 8 , and r 14 . the dynamic current sink is controlled by voltage level sensing. f or purposes of explanation, it is assumed that output terminal 6 is quiescently established at the potential midpoint between the v+ and v- supply rails. when output current sinking mode operation is required, the collector potential of transistor q 13 is driven below its quiescent level, thereby causing q 17 , q 18 to decrease the output voltage at terminal 6. thus, the gate terminal of pmos transistor q 21 is displaced toward the v- bus, thereby reducing the channel resistance of q 21 . as a consequence, there is an incremental increase in current ?w through q 20 , r 12 , q 21 , d 6 , r 7 , and the base of q 16 . as a result, q 16 sinks current from terminal 6 in direct response to the incremental change in output voltage caused by q 18 . this sink current ?ws regardless of load; any excess current is internally supplied by the emitter-follower q 18 . short circuit protection of the output circuit is provided by q 19 , which is driven into conduction by the high voltage drop developed across r 11 under output short circuit conditions. under these conditions, the collector of q 19 diverts current from q 4 so as to reduce the base current drive from q 17 , thereby limiting current ?w in q 18 to the short circuited load terminal. bias circuit quiescent current in all stages (except the dynamic current sink) of the ca3140 is dependent upon bias current ?w in r 1 . the function of the bias circuit is to establish and maintain constant current ?w through d 1 , q 6 , q 8 and d 2 . d 1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of q 1 , q 2 , and q 3 . d 1 may be considered as a current sampling diode that senses the emitter current of q 6 and automatically adjusts the base current of q 6 (via q 1 ) to maintain a constant current through q 6 , q 8 , d 2 . the base currents in q 2 , q 3 are also determined by constant current ?w d 1 . furthermore, current in diode connected transistor q 2 establishes the currents in transistors q 14 and q 15 . t ypical applications wide dynamic range of input and output characteristics with the most desirable high input impedance characteristics is achieved in the ca3140 by the use of an unique design based upon the pmos bipolar process. input common mode voltage r ange and output swing capabilities are complementary, allowing operation with the single supply down to 4v. the wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example, where one input is driven below the potential of terminal 4 and the phase sense of the output signal must be maintained ?a most important consideration in comparator applications. ca3140, ca3140a
6 output circuit considerations excellent interfacing with ttl circuitry is easily achieved with a single 6.2v zener diode connected to terminal 8 as shown in figure 1. this connection assures that the maximum output signal swing will not go more positive than the zener v oltage minus two base-to-emitter voltage drops within the ca3140. these voltages are independent of the operating supply voltage. figure 2 shows output current sinking capabilities of the ca3140 at various supply voltages. output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level shifting circuitry usually associated with the 741 series of operational ampli?rs. figure 4 shows some typical con?urations. note that a series resistor, r l , is used in both cases to limit the drive av ailable to the driven device. moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. offset voltage nulling the input offset voltage can be nulled by connecting a 10k ? potentiometer between terminals 1 and 5 and returning its wiper arm to terminal 4, see figure 3a. this technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. typical values of series resistors (r) that may be placed at either end of the potentiometer, see figure 3b, to optimize its utilization range are given in the electrical speci?ations table. an alternate system is shown in figure 3c. this circuit uses only one additional resistor of approximately the value shown in the table. for potentiometers, in which the resistance does not drop to 0 ? at either end of rotation, a v alue of resistance 10% lower than the values shown in the table should be used. low voltage operation operation at total supply voltages as low as 4v is possible with the ca3140. a current regulator based upon the pmos threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages. the low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the v oltage at terminal 4. this limit is reached at a total supply v oltage just below 4v. the output voltage range also begins to e xtend down to the negative supply rail, but is slightly higher than that of the input. figure 8 shows these characteristics and shows that with 2v dual supplies, the lower extreme of the input common mode voltage range is below ground potential. 3 2 4 ca3140 8 6 7 v+ 5v to 36v 6.2v 5v logic supply 5v typical ttl gate figure 1. zener clamping diode connected to terminals 8 and 4 to limit ca3140 output swing to ttl levels 1 0.01 0.1 load (sinking) current (ma) 1.0 10 10 100 1000 output stage transistor (q 15 , q 16 ) saturation voltage (mv) supply voltage (v-) = 0v t a = 25 o c supply voltage (v+) = +5v +15v +30v figure 2. voltage across output transistors (q 15 and q 16 ) vs load current figure 3a. basic figure 3b. improved resolution figure 3c. simpler improved resolution figure 3. three offset voltage nulling methods 3 2 4 ca3140 7 6 v+ 5 1 v- 10k ? 3 2 4 ca3140 7 6 v+ 5 1 v- 10k ? r r 3 2 4 ca3140 7 6 v+ 5 1 v- 10k ? r ca3140, ca3140a
7 bandwidth and slew rate f or those cases where bandwidth reduction is desired, for e xample, broadband noise reduction, an external capacitor connected between terminals 1 and 8 can reduce the open loop -3db bandwidth. the slew rate will, however, also be proportionally reduced by using this additional capacitor. thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. figure 5 shows the typical settling time required to reach 1mv or 10mv of the ?al value for various levels of large signal inputs for the voltage follower and inverting unity gain ampli?rs. the exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the ca3140; as shown in figure 6. input circuit considerations as mentioned previously, the ampli?r inputs can be driven below the terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1ma to prevent damage to the input protection circuitry. moreover, some current limiting resistance should be provided between the inverting input and the output when the ca3140 is used as a unity gain voltage follower. this resistance prevents the possibility of extremely large input figure 4. methods of utilizing the v ce(sat) sinking current capability of the ca3140 series figure 5a. waveform figure 5b. test circuits figure 5. settling time vs input voltage 3 2 4 ca3140 7 6 load r l r s mt 2 mt 1 30v no load 120v ac 3 2 4 ca3140 7 6 v+ +hv load r l settling time ( s) 0.1 input voltage (v) 1.0 10 supply voltage: v s = 15v t a = 25 o c 1mv 10mv 10mv 1mv 1mv 1mv 10mv follower inverting load resistance (r l ) = 2k ? load capacitance (c l ) = 100pf 10 8 6 4 2 0 -2 -4 -6 -8 -10 10mv 3 2 ca3140 6 simulated load 4 -15v 0.1 f 5.11k ? 0.1 f 7 +15v 5k ? 2k ? 100pf 5k ? inverting settling point 200 ? 4.99k ? d 1 1n914 d 2 1n914 2 ca3140 6 simulated load 4 -15v 0.1 f 0.1 f 7 +15v 2k ? 100pf 0.05 f 2k ? 3 10k ? follower ca3140, ca3140a
8 signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. a 3.9k ? resistor is suf?ient. the typical input current is on the order of 10pa when the inputs are centered at nominal device dissipation. as the output supplies load current, device dissipation will increase, r aising the chip temperature and resulting in increased input current. figure 7 shows typical input terminal current versus ambient temperature for the ca3140. it is well known that mosfet devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures. both applied voltage and temperature accelerate these changes. the process is reversible and offset voltage shifts of the opposite polarity reverse the offset. figure 9 shows the typical offset voltage change as a function of various stress v oltages at the maximum rating of 125 o c (for metal can); at lower temperatures (metal can and plastic), for example, at 85 o c, this change in voltage is considerably less. in typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational ampli?r employing a bipolar transistor input stage. figure 6. open loop voltage gain and phase vs frequency figure 7. input current vs temperature figure 8. output voltage swing capability and common mode input voltage range vs supply voltage 10 1 10 3 10 4 10 5 10 6 10 7 10 8 frequency (hz) o pen l oo p v o lta g e g ain ( db ) 100 80 60 40 20 0 supply voltage: v s = 15v t a = 25 o c 10 2 open loop phase -75 -90 -105 -120 -135 -150 (degrees) r l = 2k ? , c l = 0pf r l = 2k ? , c l = 100pf ol supply voltage: v s = 15v temperature ( o c) -60 -40 -20 0 20 40 60 80 100 120 140 input current (pa) 1k 100 1 10k 10 supply voltage (v+, v-) 0510 15 20 25 -1.5 -2.0 -1.0 -2.5 r l = +v out at t a = 125 o c +v out at t a = 25 o c +v out at t a = -55 o c +v icr at t a = 125 o c +v icr at t a = 25 o c +v icr at t a = -55 o c -3.0 0 -0.5 input and o utput v o lta g e ex c ur s i o n s from terminal 7 (v+) supply voltage (v+, v-) 0510 15 20 25 -v icr at t a = 125 o c -v icr at t a = 25 o c -v icr at t a = -55 o c -v out for t a = -55 o c to 125 o c input and output voltage excursions from terminal 4 (v-) 0 -0.5 0.5 -1.0 -1.5 1.5 1.0 ca3140, ca3140a
9 super sweep function generator a function generator having a wide tuning range is shown in figure 10. the 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary sweeping signal. the ca3140 functions as a non- inverting readout ampli?r of the triangular signal developed across the integrating capacitor network connected to the output of the ca3080a current source. buffered triangular output signals are then applied to a second ca3080 functioning as a high speed hysteresis s witch. output from the switch is returned directly back to the input of the ca3080a current source, thereby, completing the positive feedback loop the triangular output level is determined by the four 1n914 level limiting diodes of the second ca3080 and the resistor divider network connected to terminal no. 2 (input) of the ca3080. these diodes establish the input trip level to this s witching stage and, therefore, indirectly determine the amplitude of the output triangle. compensation for propagation delays around the entire loop is provided by one adjustment on the input of the ca3080. this adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sw eeping. high frequency ramp linearity is adjusted by the single 7pf to 60pf capacitor in the output of the ca3080a. it must be emphasized that only the ca3080a is characterized for maximum output linearity in the current generator function. meter driver and buffer ampli?r figure 11 shows the ca3140 connected as a meter driver and buffer ampli?r. low driving impedance is required of the ca3080a current source to assure smooth operation of the frequency adjustment control. this low-driving impedance requirement is easily met by using a ca3140 connected as a voltage follower. moreover, a meter may be placed across the input to the ca3080a to give a logarithmic analog indication of the function generators frequency. analog frequency readout is readily accomplished by the means described above because the output current of the ca3080a varies approximately one decade for each 60mv change in the applied voltage, v abc (voltage between te r minals 5 and 4 of the ca3080a of the function generator). therefore, six decades represent 360mv change in v abc . now, only the reference voltage must be established to set the lower limit on the meter. the three remaining transistors from the ca3086 array used in the sweep generator are used for this reference voltage. in addition, this reference generator arrangement tends to track ambient temperature va r iations, and thus compensates for the effects of the normal negative temperature coef?ient of the ca3080a v abc terminal voltage. another output voltage from the reference generator is used to insure temperature tracking of the lower end of the f requency adjustment potentiometer. a large series resistance simulates a current source, assuring similar temperature coef?ients at both ends of the frequency adjustment control. to calibrate this circuit, set the frequency adjustment p otentiometer at its low end. then adjust the minimum f requency calibration control for the lowest frequency. to establish the upper frequency limit, set the frequency adjustment potentiometer to its upper end and then adjust the maximum frequency calibration control for the maximum frequency. because there is interaction among these controls, repetition of the adjustment procedure may be necessary. two adjustments are used for the meter. the meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. thus, the meter sensitivity adjustment control calibrates the meter so that it de?cts 1 / 6 of full scale for each decade change in frequency. sine wave shaper the circuit shown in figure 12 uses a ca3140 as a voltage f ollower in combination with diodes from the ca3019 array to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% thd. the basic zero crossing slope is established by the 10k ? potentiometer connected between terminals 2 and 6 of the ca3140 and the 9.1k ? resistor and 10k ? potentiometer from terminal 2 to ground. two break points are established by diodes d 1 through d 4 . p ositive feedback via d 5 and d 6 establishes the zero slope at the maximum and minimum levels of the sine wave. this technique is necessary because the voltage follower con?uration approaches unity gain r ather than the zero gain required to shape the sine wave at the two extremes. 7 6 5 4 3 2 0 offset voltage shift (mv) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 time (hours) 1 differential dc voltage (across terminals 2 and 3) = 0v output voltage = v+ / 2 t a = 125 o c for metal can packages differential dc voltage (across terminals 2 and 3) = 2v output stage toggled figure 9. typical incremental offset voltage shift vs operating life ca3140, ca3140a
10 figure 10a. circuit t op trace: output at junction of 2.7 ? and 51 ? resistors; 5v/div., 500ms/div. center trace: external output of triangular function generator; 2v/div., 500ms/div. bottom trace: output of ?og generator; 10v/div., 500ms/div. figure 10b. figure function generator sweeping 1v/div., 1s/div. three tone test signals, highest frequency 0.5mhz. note the slight asymmetry at the three second/cycle signal. this asymmetry is due to slightly different positive and negative integration from the ca3080a and from the pc board and component leakages at the 100pa level. figure 10c. function generator with fixed frequencies figure 10d. interconnections figure 10. function generator 0.1 f 1n914 6 7 4 2 3 0.1 f 5.1k ? 10k ? 2.7k ? 6 7 4 2 5 -15v 13k ? +15v centering 10k ? -15v 910k ? 62k ? 11k ? 10k ? external output 11k ? high frequency level 7-60pf external output to output amplifier output amplifier to sine wave shaper 2k ? frequency adjustment high freq. shape symmetry this network is used when the optional buffer circuit is not used -15v +15v 10k ? 120 ? 39k ? 100k ? 3 6 3 2 4 7 7.5k ? +15v +15v 15k ? 360 ? 360 ? 2m ? 7-60 pf -15v -15v +15v 51 pf + ca3080a - ca3140 ca3080 + - + - 5 -15v from buffer meter driver (optional) frequency adjustment meter driver and buffer amplifier function generator sine wave shaper m power supply 15v -15v +15v dc level adjust 51 ? wideband line driver sweep generator gate sweep v- sweep length external input off v- coarse rate fine rate ext. int. ca3140, ca3140a
11 figure 11. meter driver and buffer amplifier figure 12. sine wave shaper figure 13. sweeping generator frequency calibration minimum 200 a meter frequency calibration maximum meter sensitivity adjustment meter position adjustment ca3080a 6 3 2 4 7 + ca3140 - frequency adjustment 10k ? 620 ? 4.7k ? 0.1 f 12k ? 2k ? 500k ? 620k ? 51k ? 3m ? 510 ? 510 ? 2k ? 3.6k ? -15v m 11 14 13 3 / 5 of ca3086 5 4 to c a3080a of function generator (figure 10) 7 8 6 9 1k ? 2.4k ? 2.5 k ? +15v sweep in 10 12 6 3 2 4 7 + ca3140 - 7 2 8 5 6 1 4 3 9 5.1k ? 0.1 f -15v d 1 d 4 d 2 d 3 d 6 d 5 ca3019 diode array external output +15v +15v -15v 100 k ? substrate of ca3019 to wideband output amplifier 7.5k ? 5.6k ? -15v r3 10k ? 10k ? 0.1 f 1m ? 9.1k ? r 1 10k ? r 2 1k ? 430 ? f 0.1 f coarse rate sawtooth symmetry 0.47 f 0.047 f 4700pf 470pf 7 3 2 6 4 + ca3140 - 5 1 3 2 4 1 5 51k ? 6.8k ? 91k ? 10k ? 100 ? 390 ? 3.9 ? 25k ? +15v -15v 10k ? 10k ? 100k ? 30k ? 43k ? log vio 50k ? log rate 10k ? gate pulse output -15v external output to function generator ?weep in sweep width to output amplifier 36k ? 51k ? 75k ? 50k ? sawtooth ?og triangle +15v +15v 4 7 + ca3140 - 3 2 6 +15v transistors from ca3086 array adjust triangle sawtooth ?og 8.2k ? 100k ? 100k ? fine rate sawtooth 22m ? 1m ? 18m ? 750k ? ?og 1n914 1n914 sawtooth and ramp low level set (-14.5v) -15v ca3140, ca3140a
12 this circuit can be adjusted most easily with a distortion analyzer, but a good ?st approximation can be made by comparing the output signal with that of a sine wave generator. the initial slope is adjusted with the potentiometer r 1 , followed by an adjustment of r 2 . the ?al slope is established by adjusting r 3 , thereby adding additional segments that are contributed by these diodes. because there is some interaction among these controls, repetition of the adjustment procedure may be necessary. sweeping generator figure 13 shows a sweeping generator. three ca3140s are used in this circuit. one ca3140 is used as an integrator, a second device is used as a hysteresis switch that determines the starting and stopping points of the sweep. a third ca3140 is used as a logarithmic shaping network for the log function. rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are generated by this circuit. wideband output ampli?r figure 14 shows a high slew rate, wideband ampli?r suitable for use as a 50 ? transmission line driver. this circuit, when used in conjunction with the function generator and sine wave shaper circuits shown in figures 10 and 12 provides 18v p-p output open circuited, or 9v p-p output when terminated in 50 ? . the slew rate required of this ampli?r is 28v/ s (18v p-p x x 0.5mhz). po wer supplies high input impedance, common mode capability down to the negative supply and high output drive current capability are key factors in the design of wide range output voltage supplies that use a single input voltage to provide a regulated output voltage that can be adjusted from essentially 0v to 24v. unlike many regulator systems using comparators having a bipolar transistor input stage, a high impedance reference v oltage divider from a single supply can be used in connection with the ca3140 (see figure 15). essentially, the regulators, shown in figures 16 and 17, are connected as non inverting power operational ampli?rs with a gain of 3.2. an 8v reference input yields a maximum output v oltage slightly greater than 25v. as a voltage follower, when the reference input goes to 0v the output will be 0v. because the offset voltage is also multiplied by the 3.2 gain factor, a potentiometer is needed to null the offset voltage. series pass transistors with high i cbo levels will also prevent the output voltage from reaching zero because there is a ?ite voltage drop (v cesat ) across the output of the ca3140 (see figure 2). this saturation voltage level may indeed set the lowest voltage obtainable. the high impedance presented by terminal 8 is advantageous in effecting current limiting. thus, only a small signal transistor is required for the current-limit sensing ampli?r. resistive decoupling is provided for this transistor to minimize damage to it or the ca3140 in the event of unusual input or output transients on the supply rail. figures 16 and 17, show circuits in which a d2201 high speed diode is used for the current sensor. this diode was chosen f or its slightly higher forward voltage drop characteristic, thus giving greater sensitivity. it must be emphasized that heat sinking of this diode is essential to minimize variation of the current trip point due to internal heating of the diode. that is, 1a at 1v forward drop represents one watt which can result in signi?ant regenerative changes in the current trip point as the diode temperature rises. placing the small signal reference ampli?r in the proximity of the current sensing diode also helps minimize the variability in the trip level due to the negative temperature coef?ient of the diode. in spite of those limitations, the current limiting point can easily be adjusted ov er the range from 10ma to 1a with a single adjustment potentiometer. if the temperature stability of the current limiting system is a serious consideration, the more usual current sampling resistor type of circuitry should be employed. a power darlington transistor (in a metal can with heatsink), is used as the series pass element for the conventional current limiting system, figure 16, because high power darlington dissipation will be encountered at low output v oltage and high currents. 2 6 8 1 4 7 + ca3140 - 50 f 25v 2.2 k ? 2n3053 1n914 2.2 k ? 1n914 2.7 ? 2.7 ? 2n4037 + - + - 50 f 25v 3 signal level adjustment 2.5k ? 200 ? 2.4pf 2pf -15v +15v output dc level adjustment -15v +15v 3k ? 200 ? 1.8k ? 51 ? 2w out nominal bandwidth = 10mhz t r = 35ns figure 14. wideband output amplifier 6 3 2 4 7 + ca3140 - vo ltage reference vo ltage adjustment regulated output input figure 15. basic single supply voltage regulator showing voltage follower configuration ca3140, ca3140a
13 a small heat sink versawatt transistor is used as the series pass element in the fold back current system, figure 17, since dissipation levels will only approach 10w. in this system, the d2201 diode is used for current sampling. f oldback is provided by the 3k ? and 100k ? divider network connected to the base of the current sensing transistor. both regulators provide better than 0.02% load regulation. because there is constant loop gain at all voltage settings, the regulation also remains constant. line regulation is 0.1% per v olt. hum and noise voltage is less than 200 v as read with a meter having a 10mhz bandwidth. figure 18a shows the turn on and turn off characteristics of both regulators. the slow turn on rise is due to the slow r ate of rise of the reference voltage. figure 18b shows the transient response of the regulator with the switching of a 20 ? load at 20v output. figure 16. regulated power supply figure 17. regulated power supply with ?oldback current limiting 5v/div., 1s/div. figure 18a. supply turn-on and turnoff characteristics t op trace: output voltage; 200mv/div., 5 s/div. bottom trace: collector of load switching transistor, load = 1a; 5v/div., 5 s/div. figure 18b. transient response figure 18. waveforms of dynamic characteristics of power supply currents shown in figures 16 and 17 1 3 75 ? 3k ? 100 ? 2 1k ? 1k ? d2201 current limiting adjust 2n6385 power darlington 2 1k ? 1 3 8 2n2102 1k ? +30v input 4 ca3140 7 1 6 5 100k ? 2 3 180k ? 56pf 1k ? 82k ? 250 f + - 0.01 f 100k ? 14 10 6 9 8 50k ? 13 5 f + - 12 ca3086 2.2k ? 3 1 5 4 62k ? vo ltage adjust 10 f + - 2.7k ? 1k ? 11 7 2 hum and noise output <200 v rms (measurement bandwidth ~ 10mhz) line regulation 0.1%/v load regulation (no load to full load) <0.02% output 0.1 ? 24v at 1a 1 2 1k ? 200 ? d2201 ?oldback current limiter 2n5294 3k ? 8 2n2102 1k ? +30v input 4 ca3140 7 1 6 5 100k ? 2 3 180k ? 56pf 1k ? 82k ? 250 f + - 0.01 f 100k ? 14 10 6 9 8 50k ? 13 5 f + - 12 ca3086 2.2k ? 3 1 5 4 62k ? vo ltage adjust 10 f + - 2.7k ? 1k ? 11 7 2 hum and noise output <200 v rms (measurement bandwidth ~ 10mhz) line regulation 0.1%/v load regulation (no load to full load) <0.02% output ? 0v to 25v 25v at 1a 3 100k ? ?olds back to 40ma 100k ? ca3140, ca3140a
14 t one control circuits high slew rate, wide bandwidth, high output voltage capability and high input impedance are all characteristics required of tone control ampli?rs. two tone control circuits that exploit these characteristics of the ca3140 are shown in figures 19 and 20. the ?st circuit, shown in figure 20, is the baxandall tone control circuit which provides unity gain at midband and uses standard linear potentiometers. the high input impedance of the ca3140 makes possible the use of low- cost, low-value, small size capacitors, as well as reduced load of the driving stage. bass treble boost and cut are 15db at 100hz and 10khz, respectively. full peak-to-peak output is available up to at least 20khz due to the high slew rate of the ca3140. the ampli?r gain is 3db down from its at position at 70khz. figure 19 shows another tone control circuit with similar boost and cut speci?ations. the wideband gain of this circuit is equal to the ultimate boost or cut plus one, which in this case is a gain of eleven. for 20db boost and cut, the input loading of this circuit is essentially equal to the value of the resistance from terminal no. 3 to ground. a detailed analysis of this circuit is given in ?n ic operational tr ansconductance ampli?r (ota) with power capability by l. kaplan and h. wittlinger, ieee transactions on broadcast and television receivers, vol. btr-18, no. 3, august, 1972. figure 19. tone control circuit using ca3130 series (20db midband gain) figure 20. baxandall tone control circuit using ca3140 series 4 7 + ca3140 - +30v 3 2 0.1 f 6 0.005 f 0.1 f 2.2m ? 2.2m ? 5.1 m ? 0.012 f 0.001 f 0.022 f 2 f 18k ? 0.0022 f 200k ? (linear) 100 pf 100pf boost treble cut boost bass cut 10k ? 1m ? ccw (log) 100k ? tone control network for single supply - + +15v 3 0.1 f 0.005 f 5.1m ? 0.1 f -15v 2 6 7 4 + ca3140 - tone control network for dual supplies notes: 5. 20db flat position gain. 6. 15db bass and treble boost and cut at 100hz and 10khz, respectively. 7. 25v p-p output at 20khz. 8. -3db at 24khz from 1khz reference. 4 7 + ca3140 - +32v 3 0.1 2.2m ? 2.2 m ? for single supply f 6 2 0.1 f 20pf 750 pf 750 pf 2.2m ? 0.047 f boost treble cut 51k ? 5m ? (linear) 51k ? tone control network boost bass cut 240k ? 5m ? (linear) 240k ? +15v 3 0.1 f 0.047 f 0.1 f -15v 2 6 7 4 + ca3140 - for dual supplies ???? : 9. 15db bass and treble boost and cut at 100hz and 10khz, respectively. 10. 25v p-p output at 20khz. 11. -3db at 70khz from 1khz reference. 12. 0db flat position gain. tone control network ca3140, ca3140a
15 wien bridge oscillator another application of the ca3140 that makes excellent use of its high input impedance, high slew rate, and high voltage qualities is the wien bridge sine wave oscillator. a basic wien bridge oscillator is shown in figure 21. when r 1 = r 2 = r and c 1 = c 2 = c, the frequency equation reduces to the f amiliar f = 1/(2 rc) and the gain required for oscillation, a osc is equal to 3. note that if c 2 is increased by a factor of f our and r 2 is reduced by a factor of four, the gain required f or oscillation becomes 1.5, thus permitting a potentially higher operating frequency closer to the gain bandwidth product of the ca3140. oscillator stabilization takes on many forms. it must be precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. the element, r s , is commonly replaced with some variable resistance element. thus, through some control means, the v alue of r s is adjusted to maintain constant oscillator output. a fet channel resistance, a thermistor, a lamp bulb, or other device whose resistance increases as the output amplitude is increased are a few of the elements often utilized. figure 22 shows another means of stabilizing the oscillator with a zener diode shunting the feedback resistor (r f of figure 21). as the output signal amplitude increases, the z ener diode impedance decreases resulting in more f eedback with consequent reduction in gain; thus stabilizing the amplitude of the output signal. furthermore, this combination of a monolithic zener diode and bridge recti?r circuit tends to provide a zero temperature coef?ient for this regulating system. because this bridge recti?r system has no time constant, i.e., thermal time constant for the lamp b ulb, and rc time constant for ?ters often used in detector networks, there is no lower frequency limit. for example, with 1 f polycarbonate capacitors and 22m ? for the frequency determining network, the operating frequency is 0.007hz. as the frequency is increased, the output amplitude must be reduced to prevent the output signal from becoming slew- r ate limited. an output frequency of 180khz will reach a slew r ate of approximately 9v/ s when its amplitude is 16v p-p . simple sample-and-hold system figure 23 shows a very simple sample-and-hold system using the ca3140 as the readout ampli?r for the storage capacitor. the ca3080a serves as both input buffer ampli?r and low feed-through transmission switch (see note 13). system offset nulling is accomplished with the ca3140 via its offset nulling terminals. a typical simulated load of 2k ? and 30pf is shown in the schematic. in this circuit, the storage compensation capacitance (c 1 ) is only 200pf. larger value capacitors provide longer ?old periods but with slower slew rates. the slew rate is: note: 13. an6668 ?pplications of the ca3080 and ca 3080a high performance operational transconductance amplifiers? notes: f 1 2 r 1 c 1 r 2 c 2 ------------------------------------------ - = a osc 1 c 1 c 2 ------ - r 2 r 1 ------ - ++ = a cl 1 r f r s ------- - + = c 1 r 2 r 1 c 2 output r f r s + - figure 21. basic wien bridge oscillator circuit using an operational amplifier 8 5 4 3 1 9 6 ca3109 diode array +15v 0.1 f 0.1 f -15v 2 6 7 4 + ca3140 - substrate of ca3019 0.1 f 7 7.5k ? 3.6k ? 500 ? output 19v p-p to 22v p-p thd <0.3% 3 r 2 c 2 1000pf 1000 pf c 1 r 1 r 1 = r 2 = r 50hz, r = 3.3m ? 100hz, r = 1.6m ? 1khz, r = 160m ? 10khz, r = 16m ? 30khz, r = 5.1m ? 2 figure 22. wien bridge oscillator circuit using ca3140 +15v 3.5k ? 30pf 2 6 1 + ca3140 - simulated load not required 100k ? input 0.1 0.1 f f 7 0.1 f -15v 2k ? 3 400 ? 200pf 6 4 5 7 4 + ca3080a - 0.1 f +15v -15v 200pf 2k ? 2 3 5 2k ? strobe sample hold -15 0 30k ? 1n914 1n914 2k ? c 1 figure 23. sample and hold circuit dv dt ------ i c --- - 0. 5ma 200pf 2.5v s == = ca3140, ca3140a
16 pulse ?roop during the hold interval is 170pa/200pf which is 0.85 v/ s; (i.e., 170pa/200pf). in this case, 170pa represents the typical leakage current of the ca3080a when strobed off. if c 1 were increased to 2000pf, the ?old-droop rate will decrease to 0.085 v/ s, but the slew rate would decrease to 0.25v/ s. the parallel diode network connected between te r minal 3 of the ca3080a and terminal 6 of the ca3140 prevents large input signal feedthrough across the input terminals of the ca3080a to the 200pf storage capacitor when the ca3080a is strobed off. figure 24 shows dynamic characteristic waveforms of this sample-and-hold system. current ampli?r the low input terminal current needed to drive the ca3140 makes it ideal for use in current ampli?r applications such as the one shown in figure 25 (see note 14). in this circuit, low current is supplied at the input potential as the power supply to load resistor r l . this load current is increased by the multiplication factor r 2 /r 1 , when the load current is monitored by the power supply meter m. thus, if the load current is 100na, with values shown, the load current presented to the supply will be 100 a; a much easier current to measure in many systems. note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor. the dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. essentially, the necessary high frequency feedback is provided by the capacitor with the dotted series resistor providing load decoupling. full wave recti?r figure 26 shows a single supply, absolute value, ideal full- wa ve recti?r with associated waveforms. during positive e xcursions, the input signal is fed through the feedback network directly to the output. simultaneously, the positive e xcursion of the input signal also drives the output terminal (no. 6) of the inverting ampli?r in a negative going e xcursion such that the 1n914 diode effectively disconnects the ampli?r from the signal path. during a negative going e xcursion of the input signal, the ca3140 functions as a normal inverting ampli?r with a gain equal to -r 2 /r 1 . when the equality of the two equations shown in figure 26 is satis?d, the full wave output is symmetrical. note: t op trace: output; 50mv/div., 200ns/div. bottom trace: input; 50mv/div., 200ns/div. t op trace: output signal; 5v/div, 2 s/div. center trace: difference of input and output signals through t ektronix ampli?r 7a13; 5mv/div., 2 s/div. bottom trace: input signal; 5v/div., 2 s/div. large signal response and settling time sampling response t op trace: output; 100mv/div., 500ns/div. bottom trace: input; 20v/div., 500ns/div. figure 24. sample and hold system dynamic characteristics waveforms +15v 2 1 100k ? 0.1 f -15v 4 5 7 + ca3140 - 0.1 f 4.3k ? 10k ? 6 3 r 1 power supply 10m ? r 2 i l r 2 r 1 m r l i l x figure 25. basic current amplifier for low current measurement systems ca3140, ca3140a
17 14. ?perational amplifiers design and applications? j. g. graeme, mcgraw-hill book company, page 308, ?egative immittance converter circuits? +15v 3 0.1 f 8 5k ? 7 1 5 6 2 r 2 r 1 10k ? r 3 1n914 10k ? 100k ? offset adjust 4 peak adjust 10k ? + ca3140 - 20v p-p input bw (-3db) = 290khz, dc output (avg) = 3.2v gain r 2 r 1 ------ - x r 3 r 1 r 2 r 3 + ---------------------------- - === r 3 xx 2 + 1x ----------------- ?? ?? r 1 = for x 0.5 5k ? 10k ? -------------- - r 2 r 1 ------ - == r 3 10k ? 0.75 0.5 ----------- ?? ?? 15k ? == output 0 input 0 figure 26. single supply, absolute value, ideal full wa ve rectifier with associated wa veforms t op trace: output; 50mv/div., 200ns/div. bottom trace: input; 50mv/div., 200ns/div. figure 28b. small signal response +15v -15v 2 7 4 + ca3140 - 3 0.01 f 0.01 f 6 1m ? noise voltage output 30.1k ? 1k ? r s bw (-3db) = 140khz to t al noise voltage (referred to input ) = 48 v (typ) figure 27. test circuit amplifier (30db gain) used for wideband noise measurement +15v -15v 2 7 4 + ca3140 - 3 0.1 f 0.1 f 6 0.05 f 2k ? 10k ? 100pf simulated load 2k ? bw (-3db) = 4.5mhz sr = 9v/ s figure 28a. test circuit input ca3140, ca3140a
18 (measurement made with tektronix 7a13 differential ampli?r.) t op trace: output signal; 5v/div., 5 s/div. center trace: difference signal; 5mv/div., 5 s/div. bottom trace: input signal; 5v/div., 5 s/div. figure 28c. input-output difference signal showing settling time figure 28. split supply voltage follower test circuit and associated waveforms t ypical performance curves figure 29. open-loop voltage gain vs supply vo lta ge and temperature figure 30. gain bandwidth product vs supply vo lta ge and temperature 125 100 75 50 25 open-loop voltage gain (db) 0510 15 20 supply voltage (v) 125 o c 25 o c t a = -55 o c r l = 2k ? 25 0 gain bandwidth product (mhz) 125 o c 25 o c t a = -55 o c r l = 2k ? 20 10 0510 15 20 supply voltage (v) 25 c l = 100pf 1 ca3140, ca3140a
19 metallization mask layout figure 31. slew rate vs supply voltage and temperature figure 32. quiescent supply current vs supply vo lta ge and temperature figure 33. maximum output voltage swing vs frequency figure 34. common mode rejection ratio vs frequency figure 35. equivalent input noise voltage vs frequency figure 36. power supply rejection ratio vs frequency t ypical performance curves (continued) 125 o c 25 o c t a = -55 o c r l = 2k ? 5101520 supply voltage (v) 25 c l = 100pf 20 15 10 5 0 slew rate (v/ s) 0 7 6 5 4 3 0510 15 20 supply voltage (v) 125 o c t a = -55 o c r l = 25 0 2 1 25 o c q uiescent supply current (ma) 25 20 15 10 5 0 output swing (v p-p ) 10k 100k frequency (hz) 1m 4m supply voltage: v s = 15v t a = 25 o c 120 100 80 60 40 20 0 common-mode rejection ratio (db) 10 1 10 2 10 3 10 4 10 5 10 6 10 7 frequency (hz) supply voltage: v s = 15v t a = 25 o c supply voltage: v s = 15v t a = 25 o c frequency (hz) 110 1 10 2 10 3 10 4 10 5 equivalent input noise voltage (nv/ h z ) 100 10 1 1000 10 2 10 3 10 4 10 5 10 6 10 7 frequency (hz) power supply rejection ratio (db) 100 80 60 40 20 0 +psrr -psrr supply voltage: v s = 15v t a = 25 o c power supply rejection ratio (psrr) = ? v io / ? v s 10 1 ca3140, ca3140a
20 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporations quality certi?ations can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft w are and/or speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. f or information regarding intersil corporation and its products, see www.intersil.com sales of?e headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. grid graduations are in mils (10 -3 inch). the photographs and dimensions represent a chip when it is part of the wafer. when the wafer is cut into chips, the cleavage angles are 57 o instead of 90 with respect to the face of the chip. therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. 62-70 (1.575-1.778) 4-10 (0.102-0.254) 60 50 40 30 20 10 0 58-66 (1.473-1.676) 50 40 30 20 10 61 0 60 65 ca3140, ca3140a

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